From 732cb06c9b652cf899e9f329ad74ec3dae3d18b2 Mon Sep 17 00:00:00 2001 From: Lei Wang Date: Thu, 6 Jul 2023 13:49:48 +0800 Subject: [PATCH] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model commit 3baf7ae63505eb1652d1e52d65798307fead8539 upstream. SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security fixes. Add version 2 of SapphireRapids CPU model with those bits enabled also. Intel-SIG: commit 3baf7ae63505 ("target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model") Backport support of SapphireRapids CPU Model version 2 Signed-off-by: Lei Wang Signed-off-by: Tao Su Message-ID: <20230706054949.66556-6-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini [ jason: amend commit log ] Signed-off-by: Jason Zeng --- target/i386/cpu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 685bfca37e..eb911b12fa 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3675,8 +3675,17 @@ static const X86CPUDefinition builtin_x86_defs[] = { .model_id = "Intel Xeon Processor (SapphireRapids)", .versions = (X86CPUVersionDefinition[]) { { .version = 1 }, - { /* end of list */ }, - }, + { + .version = 2, + .props = (PropValue[]) { + { "sbdr-ssdp-no", "on" }, + { "fbsdp-no", "on" }, + { "psdp-no", "on" }, + { /* end of list */ } + } + }, + { /* end of list */ } + } }, { .name = "Denverton", -- 2.41.0.windows.1