48 lines
1.7 KiB
Diff
48 lines
1.7 KiB
Diff
From b42ad03f9e1fcdd7cac13789038621173f754294 Mon Sep 17 00:00:00 2001
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From: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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Date: Tue, 21 Mar 2023 02:38:36 +0000
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Subject: [PATCH] hw/audio/intel-hda: fix stream reset mainline inclusion
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commit ecd5f2882fdd10f798984eb52abd00ffc78c2ef7 category: bugfix
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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---------------------------------------------------------------
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Quote from:
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High Definition Audio Specification 1.0a, section 3.3.35
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Offset 80: {IOB}SDnCTL Stream Reset (SRST): Writing a 1 causes
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the corresponding stream to be reset. The Stream Descriptor
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registers (except the SRST bit itself) ... are reset.
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Change the code to reset the Stream Descriptor Control and Status
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registers except the SRST bit.
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/757
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Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
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Message-Id: <20211226154017.6067-3-vr_qemu@t-online.de>
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Signed-off-by: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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---
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hw/audio/intel-hda.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
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index 3aa57d274e..78a47bc08c 100644
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--- a/hw/audio/intel-hda.c
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+++ b/hw/audio/intel-hda.c
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@@ -586,7 +586,7 @@ static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint3
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if (st->ctl & 0x01) {
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/* reset */
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dprint(d, 1, "st #%d: reset\n", reg->stream);
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- st->ctl = SD_STS_FIFO_READY << 24;
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+ st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET;
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}
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if ((st->ctl & 0x02) != (old & 0x02)) {
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uint32_t stnr = (st->ctl >> 20) & 0x0f;
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--
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2.27.0
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