89 lines
3.6 KiB
Diff
89 lines
3.6 KiB
Diff
From 3eaa433ca1cbee753698893b7732819ba2e31302 Mon Sep 17 00:00:00 2001
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From: Jian Wang <wangjian161@huawei.com>
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Date: Thu, 10 Feb 2022 19:43:55 +0800
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Subject: [PATCH] i386: cache passthrough: Update Intel CPUID4.EAX[25:14] based
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on vCPU topo
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On Intel target, when host cache passthrough is disabled we will
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emulate the guest caches with default values and initialize the
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shared cpu list of the caches based on vCPU topology. However when
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host cache passthrough is enabled, the shared cpu list is consistent
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with host regardless what the vCPU topology is.
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For example, when cache passthrough is enabled, running a guest
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with vThreads=1 on a host with pThreads=2, we will get that there
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are every *two* logical vCPUs sharing a L1/L2 cache, which is not
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consistent with the vCPU topology (vThreads=1).
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So let's reinitialize BITs[25:14] of Intel CPUID 4 based on the
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actual vCPU topology instead of host pCPU topology.
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Signed-off-by: Jian Wang <wangjian161@huawei.com>
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Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
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---
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target/i386/cpu.c | 27 +++++++++++++++++++++++----
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1 file changed, 23 insertions(+), 4 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 868cf3e7e8..c1fe2895fd 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -5196,7 +5196,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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{
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X86CPU *cpu = env_archcpu(env);
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CPUState *cs = env_cpu(env);
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- uint32_t die_offset;
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+ uint32_t die_offset, smt_width;
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uint32_t limit;
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uint32_t signature[3];
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X86CPUTopoInfo topo_info;
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@@ -5205,6 +5205,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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topo_info.cores_per_die = cs->nr_cores;
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topo_info.threads_per_core = cs->nr_threads;
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+ die_offset = apicid_die_offset(&topo_info);
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+ smt_width = apicid_smt_width(&topo_info);
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+
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/* Calculate & apply limits for different index ranges */
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if (index >= 0xC0000000) {
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limit = env->cpuid_xlevel2;
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@@ -5272,8 +5275,25 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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/* cache info: needed for Core compatibility */
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if (cpu->cache_info_passthrough) {
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host_cpuid(index, count, eax, ebx, ecx, edx);
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- /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
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- *eax &= ~0xFC000000;
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+ /*
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+ * QEMU gives out its own APIC IDs, never pass down bits 31..26.
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+ * Update the cache topo bits 25..14, according to the guest
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+ * vCPU topology instead of the host pCPU topology.
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+ */
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+ *eax &= ~0xFFFFC000;
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+ switch (count) {
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+ case 0: /* L1 dcache info */
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+ case 1: /* L1 icache info */
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+ case 2: /* L2 cache info */
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+ *eax |= ((1 << smt_width) - 1) << 14;
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+ break;
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+ case 3: /* L3 cache info */
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+ *eax |= ((1 << die_offset) - 1) << 14;
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+ break;
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+ default: /* end of info */
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+ *eax = *ebx = *ecx = *edx = 0;
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+ break;
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+ }
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if ((*eax & 31) && cs->nr_cores > 1) {
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*eax |= (cs->nr_cores - 1) << 26;
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}
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@@ -5298,7 +5318,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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eax, ebx, ecx, edx);
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break;
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case 3: /* L3 cache info */
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- die_offset = apicid_die_offset(&topo_info);
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if (cpu->enable_l3_cache) {
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encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
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(1 << die_offset), cs->nr_cores,
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--
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2.27.0
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