cfn/computing-offload
Code Issues Proposed changes
79c4324644
computing-offload/generic_vdpa/qemu/ppc-spelling-fixes.patch
jiangdongxu 79c4324644 add generic_vdpa basecode 
Change-Id: I2d302dda68298877c65c99147f5bf22186a59aac
2024-09-19 17:19:46 +08:00

272 lines
11 KiB
Diff
Raw Blame History

From 0adb55804594e60380450c7644a05f9cfc4ebb8a Mon Sep 17 00:00:00 2001
From: zhujun2 <zhujun2_yewu@cmss.chinamobile.com>
Date: Sun, 26 Nov 2023 18:34:45 -0800
Subject: [PATCH] ppc: spelling fixes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
mainline inclusion
commit e6a19a6477407e57b4deb61aaa497a14d7db9626
category: bugfix
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: zhujun2 <zhujun2_yewu@cmss.chinamobile.com>
---
hw/ppc/ppc.c | 2 +-
hw/ppc/prep_systemio.c | 2 +-
hw/ppc/spapr.c | 8 ++++----
hw/ppc/spapr_hcall.c | 2 +-
hw/ppc/spapr_nvdimm.c | 2 +-
hw/ppc/spapr_pci_vfio.c | 2 +-
include/hw/ppc/openpic.h | 2 +-
include/hw/ppc/spapr.h | 2 +-
target/ppc/cpu-models.h | 4 ++--
target/ppc/cpu.h | 2 +-
target/ppc/cpu_init.c | 2 +-
target/ppc/excp_helper.c | 2 +-
target/ppc/power8-pmu-regs.c.inc | 4 ++--
target/ppc/translate/vmx-impl.c.inc | 4 ++--
14 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index cf90ab7805..6396bbe523 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -745,7 +745,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env)
decr = _cpu_ppc_load_decr(env, tb_env->decr_next);
/*
- * If large decrementer is enabled then the decrementer is signed extened
+ * If large decrementer is enabled then the decrementer is signed extended
* to 64 bits, otherwise it is a 32 bit value.
*/
if (env->spr[SPR_LPCR] & LPCR_LD) {
diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c
index b2bd783248..e51da91de5 100644
--- a/hw/ppc/prep_systemio.c
+++ b/hw/ppc/prep_systemio.c
@@ -39,7 +39,7 @@
#define TYPE_PREP_SYSTEMIO "prep-systemio"
OBJECT_DECLARE_SIMPLE_TYPE(PrepSystemIoState, PREP_SYSTEMIO)
-/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
+/* Bit as defined in PowerPC Reference Platform v1.1, sect. 6.1.5, p. 132 */
#define PREP_BIT(n) (1 << (7 - (n)))
struct PrepSystemIoState {
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 3b5fd749be..7f352ceaaa 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2488,7 +2488,7 @@ static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
return;
}
- /* Detemine the VSMT mode to use: */
+ /* Determine the VSMT mode to use: */
if (vsmt_user) {
if (spapr->vsmt < smp_threads) {
error_setg(errp, "Cannot support VSMT mode %d"
@@ -3016,7 +3016,7 @@ static int spapr_kvm_type(MachineState *machine, const char *vm_type)
{
/*
* The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to
- * accomodate the 'HV' and 'PV' formats that exists in the
+ * accommodate the 'HV' and 'PV' formats that exists in the
* wild. The 'auto' mode is being introduced already as
* lower-case, thus we don't need to bother checking for
* "AUTO".
@@ -4250,7 +4250,7 @@ spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
CPUArchId *core_slot;
MachineClass *mc = MACHINE_GET_CLASS(machine);
- /* make sure possible_cpu are intialized */
+ /* make sure possible_cpu are initialized */
mc->possible_cpu_arch_ids(machine);
/* get CPU core slot containing thread that matches cpu_index */
core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
@@ -4870,7 +4870,7 @@ static void spapr_machine_2_12_class_options(MachineClass *mc)
/* We depend on kvm_enabled() to choose a default value for the
* hpt-max-page-size capability. Of course we can't do it here
- * because this is too early and the HW accelerator isn't initialzed
+ * because this is too early and the HW accelerator isn't initialized
* yet. Postpone this to machine init (see default_caps_with_cpu()).
*/
smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 222c1b6bbd..5364bbcffa 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1532,7 +1532,7 @@ static void hypercall_register_types(void)
spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS,
h_get_cpu_characteristics);
- /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
+ /* "debugger" hcalls (also used by SLOF). Note: We do -not- differentiate
* here between the "CI" and the "CACHE" variants, they will use whatever
* mapping attributes qemu is using. When using KVM, the kernel will
* enforce the attributes more strongly
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
index 91de1052f2..b111380a45 100644
--- a/hw/ppc/spapr_nvdimm.c
+++ b/hw/ppc/spapr_nvdimm.c
@@ -336,7 +336,7 @@ static target_ulong h_scm_bind_mem(PowerPCCPU *cpu, SpaprMachineState *spapr,
/*
* Currently continue token should be zero qemu has already bound
- * everything and this hcall doesnt return H_BUSY.
+ * everything and this hcall doesn't return H_BUSY.
*/
if (continue_token > 0) {
return H_P5;
diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
index 2a76b4e0b5..6326948143 100644
--- a/hw/ppc/spapr_pci_vfio.c
+++ b/hw/ppc/spapr_pci_vfio.c
@@ -77,7 +77,7 @@ int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
* call. Now we just need to check the validity of the PCI
* pass-through devices (vfio-pci) under this sphb bus.
* We have already validated that all the devices under this sphb
- * are from same iommu group (within same PE) before comming here.
+ * are from same iommu group (within same PE) before coming here.
*
* Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh:
* Rework device EEH PE determination") kernel would call
diff --git a/include/hw/ppc/openpic.h b/include/hw/ppc/openpic.h
index ebdaf8a493..44976e6b07 100644
--- a/include/hw/ppc/openpic.h
+++ b/include/hw/ppc/openpic.h
@@ -14,7 +14,7 @@ enum {
OPENPIC_OUTPUT_INT = 0, /* IRQ */
OPENPIC_OUTPUT_CINT, /* critical IRQ */
OPENPIC_OUTPUT_MCK, /* Machine check event */
- OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
+ OPENPIC_OUTPUT_DEBUG, /* Unconditional debug event */
OPENPIC_OUTPUT_RESET, /* Core reset event */
OPENPIC_OUTPUT_NB,
};
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index ee7504b976..316b80318e 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -179,7 +179,7 @@ struct SpaprMachineState {
SpaprResizeHpt resize_hpt;
void *htab;
uint32_t htab_shift;
- uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */
+ uint64_t patb_entry; /* Process tbl registered in H_REGISTER_PROC_TBL */
SpaprPendingHpt *pending_hpt; /* in-progress resize */
hwaddr rma_size;
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index 0952592759..75ea085bd5 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -63,7 +63,7 @@ enum {
/* PowerPC 405 cores */
CPU_POWERPC_405D2 = 0x20010000,
CPU_POWERPC_405D4 = 0x41810000,
- /* PowerPC 405 microcontrolers */
+ /* PowerPC 405 microcontrollers */
/* XXX: missing 0x200108a0 */
CPU_POWERPC_405CRa = 0x40110041,
CPU_POWERPC_405CRb = 0x401100C5,
@@ -93,7 +93,7 @@ enum {
#define CPU_POWERPC_440 CPU_POWERPC_440GXf
/* PowerPC 440 cores */
CPU_POWERPC_440_XILINX = 0x7ff21910,
- /* PowerPC 440 microcontrolers */
+ /* PowerPC 440 microcontrollers */
CPU_POWERPC_440EPa = 0x42221850,
CPU_POWERPC_440EPb = 0x422218D3,
CPU_POWERPC_440GPb = 0x40120440,
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e946da5f3a..26312f9d5f 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -345,7 +345,7 @@ typedef struct ppc_v3_pate_t {
/* PMU bits */
#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
-#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */
+#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Occurred */
#define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
#define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
#define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6695985e9b..986d16a24d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7023,7 +7023,7 @@ static void register_970_lpar_sprs(CPUPPCState *env)
static void register_power5p_lpar_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
- /* Logical partitionning */
+ /* Logical partitioning */
spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 17607adbe4..f66063d55c 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -312,7 +312,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/*
* new interrupt handler msr preserves existing HV and ME unless
- * explicitly overriden
+ * explicitly overridden
*/
new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index 7391851238..c58874752b 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -16,7 +16,7 @@
* Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the
* PMCs) has problem state read access.
*
- * Read acccess is granted for all PMCC values but 0b01, where a
+ * Read access is granted for all PMCC values but 0b01, where a
* Facility Unavailable Interrupt will occur.
*/
static bool spr_groupA_read_allowed(DisasContext *ctx)
@@ -33,7 +33,7 @@ static bool spr_groupA_read_allowed(DisasContext *ctx)
* Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the
* PMCs) has problem state write access.
*
- * Write acccess is granted for PMCC values 0b10 and 0b11. Userspace
+ * Write access is granted for PMCC values 0b10 and 0b11. Userspace
* writing with PMCC 0b00 will generate a Hypervisor Emulation
* Assistance Interrupt. Userspace writing with PMCC 0b01 will
* generate a Facility Unavailable Interrupt.
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 8eb8d3a067..f56f061d18 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -127,7 +127,7 @@ static void gen_stve##name(DisasContext *ctx) \
}
GEN_VR_LDX(lvx, 0x07, 0x03);
-/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
+/* As we don't emulate the cache, lvxl is strictly equivalent to lvx */
GEN_VR_LDX(lvxl, 0x07, 0x0B);
GEN_VR_LVE(bx, 0x07, 0x00, 1);
@@ -135,7 +135,7 @@ GEN_VR_LVE(hx, 0x07, 0x01, 2);
GEN_VR_LVE(wx, 0x07, 0x02, 4);
GEN_VR_STX(svx, 0x07, 0x07);
-/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
+/* As we don't emulate the cache, stvxl is strictly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F);
GEN_VR_STVE(bx, 0x07, 0x04, 1);
--
2.27.0
View Git Blame Copy Permalink