52 lines
1.8 KiB
Diff
52 lines
1.8 KiB
Diff
From dd5bf5817259ea414f40b25f4aef3864eddb9706 Mon Sep 17 00:00:00 2001
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From: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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Date: Mon, 27 Nov 2023 03:24:57 +0000
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Subject: [PATCH] target/arm: Don't set syndrome ISS for loads and stores with
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writeback mainline inclusion commit 53ae2fdef1f5661cbaa2ea571c517f98e6041cb8
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category: bugfix
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---------------------------------------------------------------
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The architecture requires that for faults on loads and stores which
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do writeback, the syndrome information does not have the ISS
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instruction syndrome information (i.e. ISV is 0). We got this wrong
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for the load and store instructions covered by disas_ldst_reg_imm9().
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Calculate iss_valid correctly so that if the insn is a writeback one
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it is false.
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220715123323.1550983-1-peter.maydell@linaro.org
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Signed-off-by: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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---
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target/arm/translate-a64.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
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index cec672f229..549a671bea 100644
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--- a/target/arm/translate-a64.c
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+++ b/target/arm/translate-a64.c
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@@ -3039,7 +3039,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
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bool is_store = false;
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bool is_extended = false;
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bool is_unpriv = (idx == 2);
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- bool iss_valid = !is_vector;
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+ bool iss_valid;
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bool post_index;
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bool writeback;
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int memidx;
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@@ -3092,6 +3092,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
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g_assert_not_reached();
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}
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+ iss_valid = !is_vector && !writeback;
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+
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if (rn == 31) {
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gen_check_sp_alignment(s);
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}
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--
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2.27.0
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