80 lines
3.1 KiB
Diff
80 lines
3.1 KiB
Diff
From c9b226f4a56bb13d4f0924ea3ce4b334e65e6db2 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Mon, 1 Aug 2022 16:21:18 +0100
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Subject: [PATCH 2/5] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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Because we weren't setting this flag, our probe of ID_AA64ZFR0
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was always returning zero. This also obviates the adjustment
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of ID_AA64PFR0, which had sanitized the SVE field.
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The effects of the bug are not visible, because the only thing that
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ID_AA64ZFR0 is used for within qemu at present is tcg translation.
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The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
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Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
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---
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target/arm/kvm64.c | 26 ++++++++++++++------------
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1 file changed, 14 insertions(+), 12 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index b7e34a4580..5b15d0582d 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -501,7 +501,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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int fdarray[3];
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bool sve_supported;
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uint64_t features = 0;
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- uint64_t t;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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@@ -521,6 +520,15 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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*/
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struct kvm_vcpu_init init = { .target = -1, };
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+ /*
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+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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+ * which is otherwise RAZ.
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+ */
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+ sve_supported = kvm_arm_sve_supported();
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+ if (sve_supported) {
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+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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+ }
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+
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if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
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return false;
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}
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@@ -648,19 +656,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = kvm_arm_sve_supported();
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-
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- /* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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- t = ahcf->isar.regs[ID_AA64PFR0];
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- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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- ahcf->isar.regs[ID_AA64PFR0] = t;
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-
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/*
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- * Before v5.1, KVM did not support SVE and did not expose
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- * ID_AA64ZFR0_EL1 even as RAZ. After v5.1, KVM still does
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- * not expose the register to "user" requests like this
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- * unless the host supports SVE.
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+ * There is a range of kernels between kernel commit 73433762fcae
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+ * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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+ * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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+ * SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.regs[ID_AA64ZFR0],
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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--
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2.27.0
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