89 lines
3.1 KiB
Diff
89 lines
3.1 KiB
Diff
From 8964f3516cab9ed0183407136aa9f0dae87c49e3 Mon Sep 17 00:00:00 2001
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From: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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Date: Wed, 23 Nov 2022 15:38:38 -0800
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Subject: [PATCH 12/29] target/hppa: Fix deposit assert from trans_shrpw_imm
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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mainline inclusion
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commit 05bfd4db08608bc4c22de729780c1f74612fbc0e
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category: bugfix
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----------------------------------------------
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Because sa may be 0,
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tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
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may attempt a zero-width deposit at bit 32, which will assert
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for TARGET_REGISTER_BITS == 32.
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Use the newer extract2 when possible, which itself includes the
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rotri special case; otherwise mirror the code from trans_shrpw_sar,
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using concat and shri.
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Cc: qemu-stable@nongnu.org
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/635
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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---
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target/hppa/translate.c | 19 ++++++++++++-------
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1 file changed, 12 insertions(+), 7 deletions(-)
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diff --git a/target/hppa/translate.c b/target/hppa/translate.c
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index 3b9744deb4..952027a28e 100644
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--- a/target/hppa/translate.c
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+++ b/target/hppa/translate.c
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@@ -140,6 +140,7 @@
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#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
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#define tcg_gen_extract_reg tcg_gen_extract_i64
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#define tcg_gen_sextract_reg tcg_gen_sextract_i64
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+#define tcg_gen_extract2_reg tcg_gen_extract2_i64
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#define tcg_const_reg tcg_const_i64
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#define tcg_const_local_reg tcg_const_local_i64
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#define tcg_constant_reg tcg_constant_i64
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@@ -234,6 +235,7 @@
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#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
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#define tcg_gen_extract_reg tcg_gen_extract_i32
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#define tcg_gen_sextract_reg tcg_gen_sextract_i32
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+#define tcg_gen_extract2_reg tcg_gen_extract2_i32
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#define tcg_const_reg tcg_const_i32
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#define tcg_const_local_reg tcg_const_local_i32
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#define tcg_constant_reg tcg_constant_i32
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@@ -3204,19 +3206,22 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
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dest = dest_gpr(ctx, a->t);
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t2 = load_gpr(ctx, a->r2);
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- if (a->r1 == a->r2) {
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+ if (a->r1 == 0) {
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+ tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
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+ } else if (TARGET_REGISTER_BITS == 32) {
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+ tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa);
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+ } else if (a->r1 == a->r2) {
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TCGv_i32 t32 = tcg_temp_new_i32();
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tcg_gen_trunc_reg_i32(t32, t2);
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tcg_gen_rotri_i32(t32, t32, sa);
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tcg_gen_extu_i32_reg(dest, t32);
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tcg_temp_free_i32(t32);
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- } else if (a->r1 == 0) {
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- tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
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} else {
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- TCGv_reg t0 = tcg_temp_new();
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- tcg_gen_extract_reg(t0, t2, sa, 32 - sa);
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- tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
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- tcg_temp_free(t0);
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+ TCGv_i64 t64 = tcg_temp_new_i64();
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+ tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]);
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+ tcg_gen_shri_i64(t64, t64, sa);
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+ tcg_gen_trunc_i64_reg(dest, t64);
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+ tcg_temp_free_i64(t64);
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}
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save_gpr(ctx, a->t, dest);
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--
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2.27.0
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