44 lines
1.6 KiB
Diff
44 lines
1.6 KiB
Diff
From cdd89390a5e8fb55515798ab4ec5ec5fd6fed32b Mon Sep 17 00:00:00 2001
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From: Tao Su <tao1.su@linux.intel.com>
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Date: Thu, 6 Jul 2023 13:49:47 +0800
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Subject: [PATCH] target/i386: Add new bit definitions of
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MSR_IA32_ARCH_CAPABILITIES
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commit 6c43ec3b206956a8a3008accafe9eb2dfd885190 upstream.
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Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
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disclosed for fixing security issues, so add those bit definitions.
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Intel-SIG: commit 6c43ec3b2069 ("target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES")
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Backport new bit definitions of MSR_IA32_ARCH_CAPABILITIES
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Reviewed-by: Igor Mammedov <imammedo@redhat.com>
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Message-ID: <20230706054949.66556-5-tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ jason: amend commit log ]
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Signed-off-by: Jason Zeng <jason zeng@intel.com>
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---
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target/i386/cpu.h | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index edbaba0d62..37c687d4d8 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -966,7 +966,11 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
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#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
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#define MSR_ARCH_CAP_TAA_NO (1U << 8)
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+#define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13)
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+#define MSR_ARCH_CAP_FBSDP_NO (1U << 14)
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+#define MSR_ARCH_CAP_PSDP_NO (1U << 15)
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#define MSR_ARCH_CAP_FB_CLEAR (1U << 17)
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+#define MSR_ARCH_CAP_PBRSB_NO (1U << 24)
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#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
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--
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2.41.0.windows.1
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