111 lines
4.1 KiB
Diff
111 lines
4.1 KiB
Diff
From 71b820dc04fbe04342d5a05be3d774c704b682ec Mon Sep 17 00:00:00 2001
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From: Quanxian Wang <quanxian.wang@intel.com>
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Date: Wed, 8 Nov 2023 12:43:11 +0800
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Subject: [PATCH] target/i386: Add support for AVX-VNNI-INT8 in CPUID
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enumeration
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commit eaaa197d5b112ea2758b54df58881a2626de3af5 upstream.
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AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform
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Sierra Forest, aims for the platform to have superior AI capabilities.
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This instruction multiplies the individual bytes of two unsigned or
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unsigned source operands, then adds and accumulates the results into the
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destination dword element size operand.
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The bit definition:
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CPUID.(EAX=7,ECX=1):EDX[bit 4]
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AVX-VNNI-INT8 is on a new feature bits leaf. Add a CPUID feature word
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FEAT_7_1_EDX for this leaf.
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Add CPUID definition for AVX-VNNI-INT8.
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Intel-SIG: commit eaaa197d5b11 target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration.
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Backport GNR and SRF ISA into QEMU-6.2
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Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-Id: <20230303065913.1246327-5-tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ Quanxian Wang: amend commit log ]
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Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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---
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target/i386/cpu.c | 22 +++++++++++++++++++++-
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target/i386/cpu.h | 3 +++
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2 files changed, 24 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index b19fb0cf87..a14284a81b 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -663,6 +663,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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#define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM
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#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
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CPUID_7_1_EAX_FSRC)
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+#define TCG_7_1_EDX_FEATURES 0
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#define TCG_7_2_EDX_FEATURES 0
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#define TCG_APM_FEATURES 0
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#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
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@@ -906,6 +907,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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},
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.tcg_features = TCG_7_2_EDX_FEATURES,
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},
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+ [FEAT_7_1_EDX] = {
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+ .type = CPUID_FEATURE_WORD,
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+ .feat_names = {
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+ NULL, NULL, NULL, NULL,
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+ "avx-vnni-int8", NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ },
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+ .cpuid = {
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+ .eax = 7,
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+ .needs_ecx = true, .ecx = 1,
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+ .reg = R_EDX,
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+ },
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+ .tcg_features = TCG_7_1_EDX_FEATURES,
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+ },
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[FEAT_8000_0007_EDX] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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@@ -5557,9 +5577,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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}
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} else if (count == 1) {
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*eax = env->features[FEAT_7_1_EAX];
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+ *edx = env->features[FEAT_7_1_EDX];
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*ebx = 0;
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*ecx = 0;
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- *edx = 0;
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} else if (count == 2) {
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*edx = env->features[FEAT_7_2_EDX];
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*eax = 0;
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 2bcc127fac..b81d77084c 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -601,6 +601,7 @@ typedef enum FeatureWord {
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FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
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FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
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FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
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+ FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */
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FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */
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FEATURE_WORDS,
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} FeatureWord;
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@@ -895,6 +896,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
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/* Support for VPMADD52[H,L]UQ */
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#define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
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+/* Support for VPDPB[SU,UU,SS]D[,S] */
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+#define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
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/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
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#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
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--
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2.27.0
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