62 lines
2.2 KiB
Diff
62 lines
2.2 KiB
Diff
From 9a56c714caaf3bf31430a769befdf92e79388dda Mon Sep 17 00:00:00 2001
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From: Quanxian Wang <quanxian.wang@intel.com>
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Date: Wed, 8 Nov 2023 12:46:00 +0800
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Subject: [PATCH] target/i386: Add support for PREFETCHIT0/1 in CPUID
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enumeration
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commit d1a1111514333e46a98b136235f71eef90d610fa upstream.
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Latest Intel platform Granite Rapids has introduced a new instruction -
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PREFETCHIT0/1, which moves code to memory (cache) closer to the
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processor depending on specific hints.
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The bit definition:
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CPUID.(EAX=7,ECX=1):EDX[bit 14]
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Add CPUID definition for PREFETCHIT0/1.
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Intel-SIG: commit d1a111151433 target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration.
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Backport GNR and SRF ISA into QEMU-6.2
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Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-Id: <20230303065913.1246327-7-tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ Quanxian Wang: amend commit log ]
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Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index d36174d689..ee243693e3 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -913,7 +913,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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"avx-vnni-int8", "avx-ne-convert", NULL, NULL,
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NULL, NULL, NULL, NULL,
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- NULL, NULL, NULL, NULL,
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+ NULL, NULL, "prefetchiti", NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 93c8bd6a13..32ecec5fa7 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -900,6 +900,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
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/* AVX NE CONVERT Instructions */
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#define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5)
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+/* PREFETCHIT0/1 Instructions */
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+#define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
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/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
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#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
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--
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2.27.0
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