139 lines
4.6 KiB
Diff
139 lines
4.6 KiB
Diff
From 42f96b9e73ff4a23fad56bc8fefea5e477ee95b9 Mon Sep 17 00:00:00 2001
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From: Jing Liu <jing2.liu@intel.com>
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Date: Wed, 16 Feb 2022 22:04:31 -0800
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Subject: [PATCH 06/10] x86: Add AMX CPUIDs enumeration
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from mainline-v7.0.0-rc0
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commit f21a48171cf3fa39532fc8553fd82e81b88b6474
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category: feature
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feature: SPR AMX support for Qemu
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bugzilla: https://gitee.com/openeuler/intel-qemu/issues/I5VHOB
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Intel-SIG: commit f21a48171cf3 ("x86: Add AMX CPUIDs enumeration")
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----------------------------------------------
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x86: Add AMX CPUIDs enumeration
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Add AMX primary feature bits XFD and AMX_TILE to
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enumerate the CPU's AMX capability. Meanwhile, add
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AMX TILE and TMUL CPUID leaf and subleaves which
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exist when AMX TILE is present to provide the maximum
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capability of TILE and TMUL.
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Signed-off-by: Jing Liu <jing2.liu@intel.com>
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Signed-off-by: Yang Zhong <yang.zhong@intel.com>
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Message-Id: <20220217060434.52460-6-yang.zhong@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Jason Zeng <jason.zeng@intel.com>
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---
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target/i386/cpu.c | 55 ++++++++++++++++++++++++++++++++++++++++---
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target/i386/kvm/kvm.c | 4 +++-
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2 files changed, 55 insertions(+), 4 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index da81e47dc3..1bc03d3eef 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -574,6 +574,18 @@ static CPUCacheInfo legacy_l3_cache = {
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#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
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#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
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+/* CPUID Leaf 0x1D constants: */
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+#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
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+#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
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+#define INTEL_AMX_BYTES_PER_TILE 0x400
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+#define INTEL_AMX_BYTES_PER_ROW 0x40
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+#define INTEL_AMX_TILE_MAX_NAMES 0x8
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+#define INTEL_AMX_TILE_MAX_ROWS 0x10
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+
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+/* CPUID Leaf 0x1E constants: */
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+#define INTEL_AMX_TMUL_MAX_K 0x10
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+#define INTEL_AMX_TMUL_MAX_N 0x40
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+
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void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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uint32_t vendor2, uint32_t vendor3)
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{
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@@ -843,8 +855,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"avx512-vp2intersect", NULL, "md-clear", NULL,
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NULL, NULL, "serialize", NULL,
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"tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
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- NULL, NULL, NULL, "avx512-fp16",
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- NULL, NULL, "spec-ctrl", "stibp",
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+ NULL, NULL, "amx-bf16", "avx512-fp16",
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+ "amx-tile", "amx-int8", "spec-ctrl", "stibp",
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NULL, "arch-capabilities", "core-capability", "ssbd",
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},
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.cpuid = {
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@@ -909,7 +921,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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"xsaveopt", "xsavec", "xgetbv1", "xsaves",
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- NULL, NULL, NULL, NULL,
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+ "xfd", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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@@ -5605,6 +5617,43 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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}
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break;
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}
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+ case 0x1D: {
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+ /* AMX TILE */
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+ *eax = 0;
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+ *ebx = 0;
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+ *ecx = 0;
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+ *edx = 0;
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+ if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
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+ break;
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+ }
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+
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+ if (count == 0) {
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+ /* Highest numbered palette subleaf */
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+ *eax = INTEL_AMX_TILE_MAX_SUBLEAF;
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+ } else if (count == 1) {
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+ *eax = INTEL_AMX_TOTAL_TILE_BYTES |
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+ (INTEL_AMX_BYTES_PER_TILE << 16);
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+ *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16);
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+ *ecx = INTEL_AMX_TILE_MAX_ROWS;
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+ }
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+ break;
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+ }
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+ case 0x1E: {
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+ /* AMX TMUL */
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+ *eax = 0;
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+ *ebx = 0;
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+ *ecx = 0;
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+ *edx = 0;
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+ if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
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+ break;
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+ }
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+
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+ if (count == 0) {
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+ /* Highest numbered palette subleaf */
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+ *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
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+ }
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+ break;
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+ }
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case 0x40000000:
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/*
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* CPUID code in kvm_arch_init_vcpu() ignores stuff
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diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
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index e7f57d05a2..60ccdec5e8 100644
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--- a/target/i386/kvm/kvm.c
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+++ b/target/i386/kvm/kvm.c
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@@ -1779,7 +1779,9 @@ int kvm_arch_init_vcpu(CPUState *cs)
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c = &cpuid_data.entries[cpuid_i++];
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}
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break;
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- case 0x14: {
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+ case 0x14:
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+ case 0x1d:
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+ case 0x1e: {
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uint32_t times;
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c->function = i;
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--
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2.27.0
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