92 lines
3.1 KiB
Diff
92 lines
3.1 KiB
Diff
From ab183c656a2bee466e7c609224cddb75b80d9d6f Mon Sep 17 00:00:00 2001
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From: Jing Liu <jing2.liu@intel.com>
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Date: Wed, 16 Feb 2022 22:04:27 -0800
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Subject: [PATCH 02/10] x86: Fix the 64-byte boundary enumeration for extended
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state
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from mainline-v7.0.0-rc0
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commit 131266b7565bd437127bd231563572696bb27235
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category: feature
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feature: SPR AMX support for Qemu
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bugzilla: https://gitee.com/openeuler/intel-qemu/issues/I5VHOB
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Intel-SIG: commit 131266b7565b ("x86: Fix the 64-byte boundary enumeration for extended state")
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-----------------------------------------------------------
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x86: Fix the 64-byte boundary enumeration for extended state
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The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
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indicate whether the extended state component locates
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on the next 64-byte boundary following the preceding state
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component when the compacted format of an XSAVE area is
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used.
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Right now, they are all zero because no supported component
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needed the bit to be set, but the upcoming AMX feature will
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use it. Fix the subleaves value according to KVM's supported
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cpuid.
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Signed-off-by: Jing Liu <jing2.liu@intel.com>
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Signed-off-by: Yang Zhong <yang.zhong@intel.com>
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Message-Id: <20220217060434.52460-2-yang.zhong@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Jason Zeng <jason.zeng@intel.com>
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---
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target/i386/cpu.c | 1 +
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target/i386/cpu.h | 6 ++++++
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target/i386/kvm/kvm-cpu.c | 1 +
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3 files changed, 8 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index d9dca1dafb..532ca45015 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -5507,6 +5507,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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const ExtSaveArea *esa = &x86_ext_save_areas[count];
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*eax = esa->size;
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*ebx = esa->offset;
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+ *ecx = esa->ecx & ESA_FEATURE_ALIGN64_MASK;
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}
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}
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break;
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index d9296a9abc..52330d1112 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -549,6 +549,11 @@ typedef enum X86Seg {
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#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
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#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
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+#define ESA_FEATURE_ALIGN64_BIT 1
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+
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+#define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
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+
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+
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/* CPUID feature words */
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typedef enum FeatureWord {
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FEAT_1_EDX, /* CPUID[1].EDX */
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@@ -1355,6 +1360,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
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typedef struct ExtSaveArea {
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uint32_t feature, bits;
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uint32_t offset, size;
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+ uint32_t ecx;
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} ExtSaveArea;
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#define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1)
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diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
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index d95028018e..ce27d3b1df 100644
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--- a/target/i386/kvm/kvm-cpu.c
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+++ b/target/i386/kvm/kvm-cpu.c
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@@ -104,6 +104,7 @@ static void kvm_cpu_xsave_init(void)
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if (sz != 0) {
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assert(esa->size == sz);
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esa->offset = kvm_arch_get_supported_cpuid(s, 0xd, i, R_EBX);
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+ esa->ecx = kvm_arch_get_supported_cpuid(s, 0xd, i, R_ECX);
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}
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}
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}
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--
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2.27.0
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