Merge "Fix wrong address width"
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Zuul
Gerrit Code Review
commit
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@ -0,0 +1,25 @@
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From 78489fa5c3e98ac9db6244a6707622b4603bf0cb Mon Sep 17 00:00:00 2001
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From: Hayde Martinez <hayde.martinez.landa@intel.com>
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Date: Thu, 11 Oct 2018 14:44:00 -0500
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Subject: [PATCH] iommu-width-fix
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Signed-off-by: Hayde Martinez <hayde.martinez.landa@intel.com>
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---
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SPECS/openvswitch.spec | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/SPECS/openvswitch.spec b/SPECS/openvswitch.spec
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index 29255d5..a3a1c87 100644
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--- a/SPECS/openvswitch.spec
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+++ b/SPECS/openvswitch.spec
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@@ -108,6 +108,7 @@ ExclusiveArch: x86_64 aarch64 ppc64le s390x
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# ovs-patches
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Patch01: run-services-as-root-user.patch
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Patch02: log-rotation-config.patch
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+Patch03: iommu-width-fix.patch
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# OVS (including OVN) backports (0 - 300)
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--
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2.7.4
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@ -5,3 +5,4 @@
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0005-log-rotation-config.patch
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0006-rpm-check-with-condition.patch
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0007-enable-mlx-pmds.patch
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0008-iommu-width-fix.patch
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131
networking/openvswitch/centos/patches/iommu-width-fix.patch
Normal file
131
networking/openvswitch/centos/patches/iommu-width-fix.patch
Normal file
@ -0,0 +1,131 @@
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--- openvswitch-2.9.0/dpdk-17.11/drivers/bus/pci/linux/pci.c 2017-11-15 18:00:28.000000000 +0000
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+++ openvswitch-2.9.0p/dpdk-17.11/drivers/bus/pci/linux/pci.c 2018-10-10 17:59:58.370080207 +0000
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@@ -576,6 +576,86 @@
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return 0;
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}
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+
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+#if defined(RTE_ARCH_X86)
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+static bool
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+pci_one_device_iommu_support_va(struct rte_pci_device *dev)
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+{
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+#define VTD_CAP_MGAW_SHIFT 16
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+#define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT)
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+#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */
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+ struct rte_pci_addr *addr = &dev->addr;
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+ char filename[PATH_MAX];
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+ FILE *fp;
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+ uint64_t mgaw, vtd_cap_reg = 0;
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+
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+ snprintf(filename, sizeof(filename),
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+ "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap",
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+ rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid,
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+ addr->function);
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+ if (access(filename, F_OK) == -1) {
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+ /* We don't have an Intel IOMMU, assume VA supported*/
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+ return true;
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+ }
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+
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+ /* We have an intel IOMMU */
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+ fp = fopen(filename, "r");
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+ if (fp == NULL) {
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+ RTE_LOG(ERR, EAL, "%s(): can't open %s\n", __func__, filename);
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+ return false;
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+ }
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+
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+ if (fscanf(fp, "%" PRIx64, &vtd_cap_reg) != 1) {
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+ RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename);
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+ fclose(fp);
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+ return false;
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+ }
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+
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+ fclose(fp);
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+
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+ mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;
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+ if (mgaw < X86_VA_WIDTH)
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+ return false;
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+
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+ return true;
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+}
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+#elif defined(RTE_ARCH_PPC_64)
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+static bool
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+pci_one_device_iommu_support_va(__rte_unused struct rte_pci_device *dev)
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+{
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+ return false;
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+}
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+#else
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+static bool
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+pci_one_device_iommu_support_va(__rte_unused struct rte_pci_device *dev)
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+{
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+ return true;
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+}
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+#endif
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+
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+/*
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+ * * All devices IOMMUs support VA as IOVA
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+ * */
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+static bool
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+pci_devices_iommu_support_va(void)
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+{
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+ struct rte_pci_device *dev = NULL;
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+ struct rte_pci_driver *drv = NULL;
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+
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+ FOREACH_DRIVER_ON_PCIBUS(drv) {
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+ FOREACH_DEVICE_ON_PCIBUS(dev) {
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+ if (!rte_pci_match(drv, dev))
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+ continue;
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+ if (!pci_one_device_iommu_support_va(dev))
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+ return false;
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+ }
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+ }
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+ return true;
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+}
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+
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+
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+
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+
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/*
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* Get iommu class of PCI devices on the bus.
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*/
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@@ -586,12 +666,7 @@
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bool is_vfio_noiommu_enabled = true;
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bool has_iova_va;
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bool is_bound_uio;
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- bool spapr_iommu =
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-#if defined(RTE_ARCH_PPC_64)
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- true;
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-#else
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- false;
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-#endif
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+ bool iommu_no_va;
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is_bound = pci_one_device_is_bound();
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if (!is_bound)
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@@ -599,13 +674,14 @@
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has_iova_va = pci_one_device_has_iova_va();
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is_bound_uio = pci_one_device_bound_uio();
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+ iommu_no_va = !pci_devices_iommu_support_va();
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#ifdef VFIO_PRESENT
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is_vfio_noiommu_enabled = rte_vfio_noiommu_is_enabled() == true ?
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true : false;
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#endif
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if (has_iova_va && !is_bound_uio && !is_vfio_noiommu_enabled &&
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- !spapr_iommu)
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+ !iommu_no_va)
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return RTE_IOVA_VA;
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if (has_iova_va) {
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@@ -614,8 +690,8 @@
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RTE_LOG(WARNING, EAL, "vfio-noiommu mode configured\n");
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if (is_bound_uio)
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RTE_LOG(WARNING, EAL, "few device bound to UIO\n");
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- if (spapr_iommu)
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- RTE_LOG(WARNING, EAL, "sPAPR IOMMU does not support IOVA as VA\n");
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+ if (iommu_no_va)
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+ RTE_LOG(WARNING, EAL, "IOMMU does not support IOVA as VA\n");
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}
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return RTE_IOVA_PA;
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