54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
From 732cb06c9b652cf899e9f329ad74ec3dae3d18b2 Mon Sep 17 00:00:00 2001
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From: Lei Wang <lei4.wang@intel.com>
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Date: Thu, 6 Jul 2023 13:49:48 +0800
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Subject: [PATCH] target/i386: Add few security fix bits in ARCH_CAPABILITIES
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into SapphireRapids CPU model
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commit 3baf7ae63505eb1652d1e52d65798307fead8539 upstream.
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SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES
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enabled, which are related to some security fixes.
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Add version 2 of SapphireRapids CPU model with those bits enabled also.
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Intel-SIG: commit 3baf7ae63505 ("target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model")
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Backport support of SapphireRapids CPU Model version 2
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Signed-off-by: Lei Wang <lei4.wang@intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Message-ID: <20230706054949.66556-6-tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ jason: amend commit log ]
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Signed-off-by: Jason Zeng <jason.zeng@intel.com>
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---
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target/i386/cpu.c | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 685bfca37e..eb911b12fa 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -3675,8 +3675,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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.model_id = "Intel Xeon Processor (SapphireRapids)",
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.versions = (X86CPUVersionDefinition[]) {
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{ .version = 1 },
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- { /* end of list */ },
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- },
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+ {
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+ .version = 2,
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+ .props = (PropValue[]) {
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+ { "sbdr-ssdp-no", "on" },
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+ { "fbsdp-no", "on" },
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+ { "psdp-no", "on" },
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+ { /* end of list */ }
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+ }
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+ },
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+ { /* end of list */ }
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+ }
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},
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{
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.name = "Denverton",
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--
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2.41.0.windows.1
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